Computer for performing non-restoring division
US5818745A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | May 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer that performs division in either floating point or integer representation according to a novel algorithm in which a divisor is subtracted from a dividend to generate a first intermediate result. A shifter shifts the intermediate result by N-bits, where N is an integer and 2.sup.N is equal to the radix, to obtain a remainder. A look-up table produces one or more multipliers based upon an upper-bit portion of the remainder and an upper-bit portion of the divisor. The divisor is multiplied by each of the one or more multiples to generate second intermediate results. Each of the secondary intermediate results is then subtracted from the remainder to generate one or more corresponding third intermediate results. A current quotient digit is selected as the largest multiplier which corresponds to the third intermediate result having the smallest possible value (as among all of the third intermediate results).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.