Semiconductor memory device and memory module using the same
US5818792A · kind A · utility
12Cited by
5References
20Claims
0Family size
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Inventors
Key dates
| Filing date | Feb 25, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Feb 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.