System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device
US5819105A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1995 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Dec 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.