Cast metal seal for semiconductor substrates and process thereof
US5821161A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | May 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/163
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to a new scheme of providing a seal for semi-conductor substrates and chip carriers. More particularly, the invention encompasses a structure and a method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal is a two layer, solder structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder structure has a thick high melting point temperature region that is attached to a cap, and a thin interconnecting region of lower melting point temperature region for sealing the substrate to the cap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.