Passivation layer of semiconductor device and method for forming the same
US5821174A · kind A · utility
6Cited by
5References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 26, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Jun 26, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A passivation layer of semiconductor device, which comprises a chrome oxide on a silicon nitride or both on and beneath a silicon nitride. The chrome oxide is deposited in a physical vapor deposition technique, relieving the compressive stress of the silicon nitride so as to prevent cracks from occurring therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.