Multi-layer gate structure
US5821623A · kind A · utility
1Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 13, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Feb 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBiotechnology
- WIPO sectorChemistry
Abstract
A method of forming a multi-layer suicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.