Asymmetric virtual ground p-channel flash cell with latid n-type pocket and method of fabrication therefor
US5822242A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Mar 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (3) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gate cores on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned between the first and second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip aligned with the first diffusion and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.