Flash memory wordline decoder with overerase repair
US5822252A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Jul 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a flash memory and decoder with overerase repair that can provide three word line voltages to overcome the overerased problems. The wordline decoder includes a wordline latch that provides a high flexibility of erasing size so that single/multiple sub-wordlines, single/multiple wordlines, single/multiple block, and whole array can be erased simultaneously. An exemplary embodiment of a flash memory wordline decoder that can provide three voltages includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes a plurality of latches coupled to the wordlines and configured to latch the wordlines and to provide one of a plurality of operational voltages on the wordlines to accomplish a predetermined operation responsive to the procedure signal. The plurality of voltage terminals are configured in a way that the high voltage required for erasure or for…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.