Circuit and method for testing a memory device with a cell plate generator having a variable current
US5822258A · kind A · utility
25Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 5, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | May 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a memory device. The method writes test data to an array of cells of the memory device during a test mode. The method calls for driving a cell plate of the memory device during at least a portion of the test with a current level that is less than the current used during normal operation. This amplifies the affect of defective cells on the cell plate voltage thereby allowing identification of unacceptably weak cells with shorter, less strenuous tests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.