Circuit for generating internal column address suitable for burst mode
US5822270A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Dec 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal column address generation circuit generates an internal column address by utilizing an asynchronous counter. The circuit includes a column address buffer for synchronizing an initially received external address with an external system clock to generate the internal column address, and for synchronizing a counting bit output signal received at an internal input node with the external system clock to generate the internal column address; and an asynchronous counter connected to an output node of the column address buffer, for generating the bit output signal having the same or opposite phase as/to a phase of the internal column address received from the column address buffer, in response to a carry generation state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.