Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors
US5822763A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Apr 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherence protocol for a multiprocessor system. Each processor in the system has an associated cache capable of storing multiple word data lines. The system also includes a plurality of main memory modules, each having an associated distributed global directory storing directory information for lines stored in the associated main memory module. Each main memory module is connected to each processor by means of a multi-stage interconnection network. When a processor attempts to over-write an individual word in a line stored in its associated cache, a write request signal is sent to the appropriate global directory, and each other processor whose cache stores a copy of the line is notified of the request. When each other processor has responded with an acknowledgement, the first processor is allowed to proceed with the write.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.