System and method for resolving contention arising from execution of cache coherency operations in a multiple cache computer system
US5822765A · kind A · utility
21Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1995 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Dec 14, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system and method having a number of cache controllers coupled to a bus. A cache controller uses a buffer operably coupled to the bus for loading information from the bus. A status bit associated with a buffer indicates the buffer status. The cache controller has logic circuitry operably coupled to the bus and the buffer. The logic circuitry responds to a certain cache coherency operation by loading the buffer and waiting during a predetermined interval for a possible retry signal before further processing the operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.