Dual ported memory for a unified memory architecture
US5822768A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 1996 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Jan 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A unified memory architecture includes a dual ported memory, core logic and a serial controller. The dual ported memory contains a random access port and a serial port to support concurrent accesses, after an initial serial port set-up time, through the serial port and the random access port. The core logic handles accesses to the random access port on the dual ported memory for all devices except the serial controller. The serial controller also accesses the dual ported memory through the random access port, and it also receives serial data, for use in a serial data operation, through the serial port. The serial controller generates a serial port load command through the random access port to effectuate the serial data transfer. The serial controller may be a graphics controller that utilizes the dual ported memory as a frame buffer. For this embodiment, the graphics controller executes screen refresh operations through use of the serial port. A serial port load command is defined for both a synchronous and an asynchronous interface for the dual ported memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.