Method of making and accessing split gate memory device
US5824584A · kind A · utility
65Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1997 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Jun 16, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/933
Abstract
A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.