Double spacer salicide MOS process and device
US5824588A · kind A · utility
19Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Sep 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A double spacer salicide MOS device structure and a process for preparing such a device. The double spacer salicide device has a LDD structure. The first sidewall spacer disposed adjacent to the gate structure of the MOS device is higher than the gate. During the salicide process, the first sidewall spacer is used to effectively isolate the gate from the source/drain. The second sidewall spacer disposed adjacent to the first sidewall spacer is used to form the LDD structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.