Integrated circuit device isolating methods including silicon spacers and oxidation barrier films
US5824594A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1997 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Apr 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76205
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device is isolated by forming a pad oxide layer on an integrated circuit substrate. A mask pattern is formed on the pad layer. The mask pattern includes sidewalls which selectively expose the pad oxide layer between the sidewalls. A silicon spacer is formed on the sidewalls. An oxidation barrier film is formed on the silicon spacer and on the exposed pad oxide layer. The integrated circuit substrate is then oxidized through the oxidation barrier film to form a device isolating layer. The oxidation barrier film on the exposed pad oxide layer is thinner than the oxidation barrier film on the sidewalls. Thus, oxidation of the silicon spacer is delayed relative to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.