Processor for performing two-dimensional inverse discrete cosine transform
US5825420A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1995 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Oct 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is provided for transforming N.times.N discrete cosine transform (DCT) coefficients F.sub.uv inputted from a run-length-code 5 (RLC) decoder and arranged in an input order into an image data f.sub.jk in an integrated circuit through a 2-D inverse discrete cosine transform (IDCT) procedure wherein subscripts u and v of DCT coefficients F.sub.uv are input frequency indices respectively having least significant bits (LSB) u.sub.0 and v.sub.0 having an exclusive-OR (XOR) and subscripts j and k of image data f.sub.jk are spatial indices generated by the integrated circuit, which comprises a cosine pre-multiplier array for computing cosine-weighted DCT coefficients, a principal subkernel mapper utilizing the cosine-weighted DCT coefficients by first referring to the indices u and v for forming a principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.uv, an N.times.N accumulating matrix operating with the principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.uv for progressively accumulating the image data f.sub.jk, and an output buffer for loading the image data f.sub.jk from the N.times.N accumulating matrix and transferring the image data f.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.