Numerically intensive computer accelerator
US5825677A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Mar 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.