Apparatus and method for maintaining status flags and condition codes using a renaming technique in an out of order floating point execution unit
US5826070A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Aug 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method reduces the number of rename registers for a floating point status and control register (FPSCR) in a superscalar microprocessor executing out of order/speculative instructions. A floating point queue (FPQ) receives speculative instructions and issues out-of-order instructions to FPQ execution units, each instruction containing a group identifier tag (GID) and a target identifier tag (TID). The GID tag indicates a set of instructions bounded by interruptible or branch instructions. The TID indicates a targeted architected facility and the program order of the instruction. The FPSCR contains status and control bits for each instruction and is updated when an instruction is executed and committed. A FPSCR renaming mechanism assigns an FPSCR rename to selected FPSCR bits during instruction dispatch from an instruction fetch unit (IFU) to the FPQ when an arithmetic instruction is dispatched that has a GID which has not been committed by instruction dispatch unit (IDU) and does not already have an FPSCR rename assigned, as determined by the FPQ. The FPSCR rename mechanism utilizes the TID upon the presence of selected bits in the FPSCR. The bits in the FPSCR renam…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.