Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation

US5827747A · kind A · utility

Assignee

• MOSEL VITELIC INC. · TW

Inventors

• Chih-Hsien Wang · Baoshan, TW
• Min-Liang Chen · Baoshan, TW

Key dates

• Filing date: Mar 28, 1996
• Grant date: Oct 27, 1998
• Expiry date: Mar 28, 2016

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.