Multiplier based on a variable radix multiplier coding
US5828590A · kind A · utility
12Cited by
5References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 27, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Nov 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/722
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modular multiplication method and device is based on RSD arithmetic, partial product reduction techniques and precomputation techniques. During multiplication, redundant representation is adopted to carry out addition of two large numbers (512 bits or longer) without carry propagation. A multiplication based on variable radix multiplier coding is performed by coding y.sub.i into a radix.sub.-- 8 digit y.sub.j, except when y.sub.j =.+-.3, in which case y.sub.i is coded into a radix.sub.-- 4 digit y.sub.j. This modular multiplication method is used for VLSI implementation of many public-key cryptosystems, such as RSA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.