Semiconductor memory device
US5828619A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Apr 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a DRAM, an external cycle count circuit detects an operation cycle of a signal RAS which is externally inputted, and a signal expressing the result is outputted to a CBR signal generating circuit and a self refresh signal generating circuit. In response to outputs from the respective signal generating circuits, an internal RAS signal generating circuit outputs a refresh instruction signal INRAS for CBR refresh and self refresh. For self refresh, as the operation cycle of the signal RAS immediately before self refresh begins, a refresh cycle is set longer. For CBR refresh, when the operation cycle of the signal RAS is long, a CBR refresh instruction signal is generated in accordance with only a part of an operation of the signal RAS. By reducing the frequency of refresh, consumption power is reduced. By means of control which considers a parameter which influences an internal temperature of a semiconductor memory device such as a DRAM, consumption power is reduced and an operation speed is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.