Data processing device equipped with cache memory and a storage unit for storing data between a main storage or CPU cache memory
US5828860A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1996 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Oct 28, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing device includes a cache memory, a load buffer primary (LBP) for storing 1-line instruction data including an instruction requested to be transmitted by an instruction processing unit and transmitted from a main storage or a secondary cache memory, and a load buffer secondary (LBS) for storing 1-line instruction data preceded by the above described 1-line data. With this configuration, the device may determine the validity of prefetched data in the LBP using lower order bits of the addresses of the data. If the data are determined to be valid, the data stored in the LBS are stored in the cache memory. A cache storage device, hierarchically provided between a central processing unit a n d a main storage device, includes a cache memory, a storage buffer, a write-in buffer and a cache storage control unit. The cache storage device fast writes storage data into a write-in buffer instead of directly into cache memory. In the case of a miss in an access to a cache tag during the execution of a load command, move-in data are read out from the main storage device or a cache storage device of a different hierarchy, for storage into a write-in buffer. The data stored in the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.