Method and structure for implementing a cache memory using a DRAM array
US5829026A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1997 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Mar 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. The DRAM array is operated at a higher frequency than the frequency of the CPU bus clock signal, thereby reducing the access latency of the DRAM array. By operating the DRAM array at a higher frequency than the CPU bus, additional time is provided for precharging the DRAM array. As a result, the precharging of the DRAM array is transparent to the CPU bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.