IGBT having a vertical channel

US5831292A · kind A · utility

Assignee

• ABB RESEARCH LTD. · CH

Inventors

• Christopher Harris · Sollentuna, SE
• Andrei Konstantinov · Linköping, SE
• Erik Janzen · Borensberg, SE

Key dates

• Filing date: Apr 24, 1996
• Grant date: Nov 3, 1998
• Expiry date: Apr 24, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8325

Abstract

A transistor of SiC having an insulated gate comprises a drain contact with a highly doped substrate layer formed on the drain. The substrate layer is of p-type or of n-type. For a p-type transistor, a highly doped n-type buffer layer may optionally be formed on top of the substrate layer. A low doped n-type drift layer, a highly doped p-type base layer, a highly doped n-type source region, and a source contact are then superimposed on the substrate layer. A vertical trench extends through the source region and the base layer to at least the drift layer. The trench has a wall next to these layers. A gate electrode extends vertically along the wall and at least over a vertical extension of the base layer. An insulating layer is arranged between the gate electrode and at least the base layer whereby an inversion channel is formed for electron transport from the source contact to the drain contact. An additional low doped p-type layer is arranged in the channel region laterally to the base layer, between the base layer and the insulating layer. The additional layer extends vertically over at least the base layer.