Multi-finger MOS transistor element
US5831316A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Jan 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A multi-finger MOS transistor element is provided in which all of the base resistance values of parasitic bipolar transistors (NPN, if an NMOS, or PNP, if a PMOS transistor) in each finger MOS are equal to each other. Thus, each finger MOS transistor element in the multi-finger MOS transistor is turned on simultaneously to enhance ESD protection performance. In the multi-finger MOS transistor, the diffusion region for providing the well/substrate contact is distributed in the source region to make the base resistance value of the parasitic NPN (or PNP) transistor in each finger MOS equal to each other. The multi-finger MOS of the invention includes a plurality of drain regions, each having drain contacts, a plurality of source regions, each having source contacts, and a plurality of gate regions, wherein each gate region is between each drain region and the source region; a bias diffusion region formed in the source region along a middle line which is equally spaced between the pair of gate regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.