MOS master-slave flip-flop with reduced number of pass gates
US5831463A · kind A · utility
11Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 13, 1996 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Aug 13, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances I.sub.DDQ -testability with respect to known flip-flops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.