Termination circuit with power-down mode for use in circuit module architecture
US5831467A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1996 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Aug 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus line termination circuit for limiting signal swing on a bus line to a reduced CMOS-swing. The termination circuit includes a switch and a first resistor connected in series between the bus line and a first voltage supply, and a second resistor connected in series between the bus line and a second voltage supply. The values of the first and second resistors are selected such that a termination voltage equal to the average of the first and second supply voltages exists on the bus line. The bus line is further connected to a receiver circuit having a threshold voltage equal to the average of the first and second supply voltages. The switch is controlled to disconnect the bus line from the first voltage supply when the bus line is in an inactive state. In an alternative embodiment, a termination circuit includes one or more voltage regulator circuits, each being coupled to the first and second voltage supplies. A clamping resistor coupled each voltage regulator circuit to the bus line. The voltage regulators are disabled when the bus line is in an inactive state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.