Design tools for high-level synthesis of a low-power data path
US5831864A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1996 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Oct 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-aided design tool and associated methods address the problem of high-level behavioral synthesis, useful in the design of semiconductor integrated circuit for minimum power consumption. The tool makes a plurality of types of power reducing changes, and evaluates the results using iterative improvement. In a particular embodiment, "moves" corresponding to alterations of scheduling of operations or resource sharing are iteratively proposed and evaluated with a power "cost function" defined by summing estimates of the switched capacitance of each resource element. In an extension of that embodiment, moves corresponding to alterations of module selection and clock selection are also evaluated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.