Memory cell
US5831896A · kind A · utility
31Cited by
13References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1996 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Dec 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A five transistor memory cell, is a single ended static random access memory (SRAM) cell. Reading and writing from the cell is implemented with one bit line along with word line read and word line write signals. One of the transistors within the memory cell is not coupled directly to ground, but is instead coupled to a controlled impedance node. This permits the affected transistor to float between ground and a high impedance state, which permits one bit line to write into the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.