Electrically erasable programmable read-only memory with threshold value controller for data programming and method of programming the same
US5831903A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Jun 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific basing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplied the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.