Techniques for reducing redundant element fuses in a dynamic random access memory array
US5831917A · kind A · utility
4Cited by
2References
24Claims
0Family size
Inventor
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/787
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array having a first plurality of fuse-sharing redundant elements for replacing defective elements of the memory array. The memory array includes a first fuse, and first group of redundant elements of the first plurality of fuse-sharing redundant elements. The first group of redundant elements share the first fuse as their highest order address fuse. The memory array further includes a second group of redundant elements of the first plurality of fuse-sharing redundant elements. The second group of redundant elements is mutually exclusive with respect to the first group of redundant elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.