Fault-tolerant memory address decoder
US5831986A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1995 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Oct 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hard-open defects between logic gates of an address decoder and the voltage supply render a memory conditionally inoperative. The decoders are therefore examined for such hard-open defects. Two cells of two logically adjacent rows or columns are written with complementary logic data. If a Read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect in the decoders is demonstrated. Alternatively, the memory is provided with a fault-tolerant decoder that comprises additional disabling circuitry to properly disable the rows and columns even when a hard-open defect is present in the decoders' logic gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.