Method and apparatus for scan chain with reduced delay penalty
US5831993A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Mar 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is provided for operating a scan chain in a semiconductor device having a plurality of serially connected logic blocks, an output from a first logic block being coupled to an input of a first latch, the output from the first latch being coupled to the input of a second logic block, an output of the second logic block being coupled to an input of a second latch, the method comprising: detecting a test enable signal; if the test enable signal is active: detecting the output of the first latch, and setting the output of the second latch to the same state as the detected output of the first latch, independently of the state of the output of the second logic block; if the test enable signal is inactive: setting the output of the second latch responsive to the output of the second logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.