Memory queue with adjustable priority and conflict detection
US5832304A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1995 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Mar 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory request storage and allocation system using parallel queues to retain different categories of memory requests until they can be acted on by the main memory. Memory requests in the parallel queues are allowed to access the main memory according to a queue priority scheme. The queue priority scheme is based on an adjustable ratio, which determines the rate at which memory requests from one queue are allowed to access the main memory versus memory requests from other queues. Registers for bypassing the adjustable ratio eliminate delays by prohibiting the queue priority circuitry from attempting to retrieve a non-existent memory request from a queue. Conflict detection circuitry maintains proper instruction order in the parallel queue architecture by ensuring that subsequent memory requests, which have the same address as a memory request already in the queue, are placed in the same queue in the order that they were entered into the queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.