Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
US5832534A · kind A · utility
27Cited by
23References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1995 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Oct 31, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache memory and a level two (L2) cache memory. In this manner, the processor is able to send operations to be performed to the L2 cache memory, such as writing state and/or cache line status to the L2 cache memory. A dedicated bus is coupled between dice. This dedicated bus is used to send control and other signals between the processor and the L2 cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.