Gurbir Singh
46Patents
20h-index
59Co-inventors
88Inventor score
Filing activity: May 7, 1987 → Nov 30, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6118306A | Changing clock frequency | Emerging Cross-Sectional Technologies | 103 | Expired |
| US5581782A | Computer system with distributed bus arbitration scheme for symmetric and priority agents | Electricity | 85 | Expired |
| US5796977A | Highly pipelined bus architecture | Physics | 69 | Expired |
| US6601121B2 | Quad pumped bus architecture and protocol | Physics | 63 | Expired |
| US6006299A | Apparatus and method for caching lock conditions in a multi-processor system | Physics | 60 | Expired |
| US6202125A | Processor-cache protocol using simple commands to implement a range of cache configurations | Physics | 60 | Expired |
| US5715428A | Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system | Physics | 59 | Expired |
| US5615343A | Method and apparatus for performing deferred transactions | Physics | 51 | Expired |
| US5568620A | Method and apparatus for performing bus transactions in a computer system | Physics | 51 | Expired |
| US5345576A | Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss | Physics | 48 | Expired |
| US5754833A | Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio | Electricity | 45 | Expired |
| US5809524A | Method and apparatus for cache memory replacement line identification | Physics | 40 | Expired |
| US6967321B2 | Optical navigation sensor with integrated lens | Physics | 39 | Expired |
| US5903908A | Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories | Emerging Cross-Sectional Technologies | 36 | Expired |
| US4803622A | Programmable I/O sequencer for use in an I/O processor | Physics | 32 | Expired |
| USRE38388E1 | Method and apparatus for performing deferred transactions | General | 29 | Expired |
| US7112916B2 | Light emitting diode based light source emitting collimated light | Emerging Cross-Sectional Technologies | 28 | Expired |
| US5832534A | Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories | Emerging Cross-Sectional Technologies | 27 | Expired |
| US6806583B2 | Light source | Electricity | 27 | Expired |
| US5701503A | Method and apparatus for transferring information between a processor and a memory system | Physics | 21 | Expired |
| US5937171A | Method and apparatus for performing deferred transactions | Physics | 20 | Expired |
| US5678020A | Memory subsystem wherein a single processor chip controls multiple cache memory chips | Physics | 20 | Expired |
| US5903738A | Method and apparatus for performing bus transactions in a computer system | Physics | 18 | Expired |
| US5911053A | Method and apparatus for changing data transfer widths in a computer system | Physics | 18 | Expired |
| US6311281A | Apparatus and method for changing processor clock ratio settings | Electricity | 18 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.