Process for fabricating low off current thin film transistor
US5834341A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 7, 1995 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Nov 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0321
Abstract
The invention is directed to a thin film transistor (TFT) wherein HF precleaning of a gate oxide layer is eliminated, thus avoiding surface degradation and maintaining the smoothness of the gate oxide layer. This results in a TFT that has low Ioff, low stand-by power, and high Ion/Ioff ratio. The invention forms a TFT by depositing a smooth surfaced TFT oxide layer over the TFT gate poly layer. The TFT gate poly layer includes a gate and a drain connection to the drain of a driver. No via hole is patterned over the TFT gate oxide before the TFT body film deposition. Therefore, no HF precleaning step is used. The TFT body layer is then deposited over the gate layer. Source and drain regions are formed in the TFT body layer. In order to connect to drain region of the TFT body layer with the drain connection in the TFT gate layer, a via is formed through the TFT drain and TFT oxide layer. Polysilicon is formed on the walls of the via to provide a conductive path from the TFT drain to the TFT drain connection of the TFT gate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.