Packing structure of semiconductor packages
US5834832A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Dec 17, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/924
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packing structure for a surface mounting type semiconductor package, wherein at least one semiconductor chips are mounted on a die pad. A conductive pattern is formed on a printed circuit board which is located beneath an exposed side of a die pad of the package. A nonconductive thin film or a conductive layer is formed between the conductive pattern and the die pad. The conductive pattern is electrically connected to the die pad so that there is generated the package voltage difference therebetween, thereby reducing the electric noise of the package and facilitating high speed operation of the package without reducing a mounting density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.