Memory system with write buffer, prefetch and internal caches
US5835945A · kind A · utility
6Cited by
15References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 1990 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Aug 6, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.