High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations
US5835946A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Apr 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.