Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same

US5837598A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Sheldon Aronowitz · San Jose, US
• Valeriy Sukharev · Cupertino, US
• Jon S. Owyang · San Jose, US
• John Haywood · Santa Clara, US

Key dates

• Filing date: Mar 13, 1997
• Grant date: Nov 17, 1998
• Expiry date: Mar 13, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/661
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e., by implantation followed by furnace annealing, to diffuse and activate the dopant in the polysilicon gate electrode without, however, resulting in penetration of the dopant through the barrier layer into the underlying gate oxide layer or the semiconductor substrate.