Insulated-gate semiconductor device
US5838026A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Mar 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.