Barrier layer for ferroelectric capacitor integrated on silicon
US5838035A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Jun 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
A ferroelectric cell in which a ferroelectric stack of a perovskite ferroelectric sandwiched by cubic perovskite metal-oxide conductive electrodes are formed over a silicon body, such as a polysilicon plug penetrating a field oxide over a silicon transistor. According to the invention, an oxidation barrier is placed between the lower metal-oxide electrode and the polysilicon. The oxidation barrier may be: (1) a refractory metal sandwiched between two platinum layer which forms a refractory oxide in a platinum matrix; (2) an intermetallic barrier beneath a platinum electrode, e.g., of NiAl; or (3) a combination of Ru and SrRuO.sub.3 or similar materials. Thereby, the polysilicon plug is protected from oxidation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.