Semiconductor memory device capable of realizing a minimum memory cell area approximate to a theoretical value

US5838036A · kind A · utility

Assignee

• NEC CORPORATION · JP

Inventor

• Hidemitsu Mori · Tokyo, JP

Key dates

• Filing date: Nov 8, 1996
• Grant date: Nov 17, 1998
• Expiry date: Nov 8, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/30

Abstract

In semiconductor memory device, word lines (2a) are arranged in parallel to each other on a semiconductor substrate (9). Each of the device active regions (1) has first oblique intersection portions (1a) which obliquely intersect adjacent two of the word lines (2a) in first oblique directions with a distance left between each of the device active regions (1) and the adjacent two of the word lines (2a). Each of bit lines (4) has second oblique intersection portions (4a) which obliquely intersect the adjacent two of the word lines (4) in second oblique directions reverse with respect to the first oblique directions with another distance left between each of the bit lines (4) and the adjacent two of the word lines (2a). The first oblique directions of the first oblique intersection portions (1a) of each of the device active regions (1) are reversed at every memory cell (or at every two memory cells). The second oblique directions of the second oblique intersection portions (4a) of each of the bit lines (4) are reversed at every memory cell (or at every two memory cells).