Nonvolatile reprogrammable interconnect cell with FN tunneling in sense
US5838040A · kind A · utility
22Cited by
12References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Mar 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.