Hexagon CMOS device
US5838050A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1997 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Sep 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A CMOS device containing a plurality of hexagon cells over a semiconductor substrate is disclosed. Each hexagon cell includes a hexagonal ring gate, a drain diffusion region and a source diffusion region. The hexagonal ring gate is made of conducting materials and a dielectric layer over the substrate, therefore defining a channel region in the substrate between the gate and the substrate. The entire drain diffusion region in the substrate is enclosed by the hexagonal ring gate. The source diffusion region surrounds the hexagonal ring gate in the substrate. Each hexagon cell further provides a drain contact in the center of the drain diffusion region. A plurality of source contacts are arranged around the ring gate over the substrate. The hexagon cells of a unique hexagon device are surrounded by a first guard ring and a second guard ring. The hexagon device can be used as a CMOS output buffer or input ESD protection circuit to reduce the layout area of an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.