Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method
US5838684A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1996 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Feb 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3018
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.