Semiconductor device having CMOS transistors
US5841185A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 15, 1996 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Feb 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a semiconductor substrate having N- and P-channel regions formed therein; a plurality of first transistors formed in the N-channel region; a first field shield element-isolation structure having a first shield plate electrode and formed in the N-channel region for isolating the first transistors from each other; a plurality of second transistors formed in the P-channel region; and a second field shield element-isolation structure having a second shield plate electrode electrically connected to the first shield plate electrode and formed in the P-channel region for isolating the second transistors from each other; wherein respective values of a threshold voltage V.sub.tN of a parasitic transistor formed in a field region of the N-channel region, a threshold voltage V.sub.tP of a parasitic transistor formed in a field region of the P-channel region and a potential V.sub.sP of the first or second shield plate electrode are determined so as to meet V.sub.tN -V.sub.tP >V.sub.cc -V.sub.ss and V.sub.tN >V.sub.sP -V.sub.ss >V.sub.tP +V.sub.cc -V.sub.ss, where V.sub.ss is a potential of the source of the first transistor, V.sub.cc is a potential of the sourc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.