Matched delay word line strap
US5841688A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1997 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Jun 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is designed with a first lower conductor (500) having two ends. One end of the first lower conductor is coupled to a first signal source (386). A first upper conductor (544) has two ends and is spaced apart from the first lower conductor by a distance less than an allowable spacing between adjacent lower conductors. One end of the first upper conductor is coupled to a second signal source (384). A second upper conductor (508) has two ends. One end of the second upper conductor is coupled to another end of the first lower conductor for receiving a signal from the first signal source. A second lower conductor (552) has two ends and is spaced apart from the second upper conductor by a distance less than the allowable spacing between adjacent lower conductors. One end of the second lower conductor is coupled to another end of the first upper conductor for receiving a signal from the second signal source. Since the upper and lower conductors are spaced apart by a distance less than an allowable spacing between adjacent lower conductors, layout area is conserved. Total resistance of conductors connected to each signal source is the same, so signal delay is the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.